Chip designer Intel last month revealed during its second-quarter earnings call that it would delay the release of its Cannonlake chips manufactured on the 10-nanometer process to the second half of 2017. The chips had been slated for launch in 2016.
The news marks a crack in Intel’s scheduling system of shrinking its transistors every two years, dubbed “Moore’s Law,” as chips become more intricate and complex to build.
“On all of these technologies, each one has its own recipe of complexity and difficulty, and 14-nanometer to 10-nanometer [is the] same thing that happened from 22-nanometer to 14-nanometer,” said Intel CEO Brian Krzanich on the call. “The lithography is continuing to get more difficult as you try and scale, and the number of multi-pattern steps you have to do is increasing.”
Intel’s upcoming sixth-generation microarchitecture, Skylake, the successor to the current Broadwell platform, will baptize a slew of 14-nanometer processors and is expected to be released at the Intel Developer Forum later this month.
The platform scheduled to be released after that, the 10-nanometer Cannonlake microarchitecture, represents a “tock” in Intel’s “tick-tock” staggered release schedule based on Moore’s Law; while the “tick” symbolises a reproduction in node size, “tock” represents a new architecture.
